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Altera_Forum's avatar
Altera_Forum
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16 years ago

Ripple clock caused by State Machines

Hi,

I'm trying to make a project, so I have 6 state machines which are related/cascaded. I have 3 state machines layers and a clock flow over those state machines as follows:

Layer 1: FSM_1........FMS_2

................|.................|

Layer 2: FSM_3........FMS_4

................|.................|

Layer 3: FSM_5<==>FMS_6

................|.................|

OBS: Do not consider any "." it was put just to help show the design schema.

FSM1/2 have four states:

type state_type is (init, wait, processData, sendData);

FSM3/4 have three states:

type state_type is (init, wait, sendCompResult);

FSM5 have five states:

type state_type is (initState, waitState, faultState, dispState, failState);

FSM6 have six states:

type state_type is (initState, inativeState, waitState, faultState, dispState, failState);

The changing of state in FSM3/4 occurs when FSM1/2 send a signal to those FSMs (FSM1 => FSM3 and FSM2 => FSM4). Then, this makes the following warnings appears, thus the circuit don't works as it should do.

Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected ripple clock "Layer2: DetecMaster|ControlUnityDetection:U01|pr_state. sendCompResult" as buffer

Info: Detected ripple clock "Layer1:AplicMaster|Processor:Proc_01|ControlUnityProcessor:U01|at_state.processData" as buffer

I have been trying hardly to solve this problem. I've look in many forums, but I didn't find a solution. How could I fix this problem? Should I use a derived clock? If yes, how can I assign one? I've been use a PLL as a clock... maybe the problem is related to some global clock, isn't it? I don't know what to do :(

Best regards,

Higor

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The answer lies in your code. Those signals you've indicated must be connected as clocks to at least one register in your design. Maybe it's intentional, maybe not.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It is normally bad practice, and bad design, to use logic to drive internal clocks inside FPGAs. It is normally much much better and much easier to debug if you use a common clock for all logic, and then use the logic to generate enable signals for other parts of the design.

    I would recommend that you use the states, and not a ripple clock, to enable the other parts of the logic.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you guys,

    I'm getting started with design and I have much much more to learn. I just want to clarify:

    Jake:

    Do you recommend to put a register between each Layer? If yes, this register wold be tigered by a global clock and to the input D should be assigned a signal come from the state machine?

    Tricky:

    How could I use those states to enable the others logic parts? each machine, it is supposed to be independent in one way. For example: If a data arrives to layer one, so it is processed and then forward to layer two. At this moment the layer one could receive others data to be processed.

    As I told you, I'm just learning yet. Please, be more clear.

    Thank you very much guys,

    Higor
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    As already said, hierarchical state machines are supposed to use a single system clock and clock enables rather than gated clocks for conditional activation of a particular state machine.

    Because the whole design is located in a single clock domain, state variables from one state machine can be directly processed in an other one, normally.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Clock everything with a single clock. Again, clock all state machines with the same clock.

    You should pass control signals (be they state variables or triggers or whatever) between state machines to synchronize their logic. For instance, one state machine can pass a "start" signal to another state machine. The "start" signal would obviously be derived from the state and possibly other conditions of the first state machine. The second state machine could then pass a "done" signal back to the first state machine to allow it to continue.

    Ripple clocks have their place but in all cases they are deliberate and by design. If you have a ripple clock show up in your design and you didn't mean to put it there, it shouldn't be there.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ok People,

    I really understand what you told me. I'm using just one clock for all those state machines. I'm not dividing or multiplying it. The design looks ok to me, I can't to figure out what it's happen to make that warning appears.

    Jake, my logic don't needs a "done" signal back. It's not necessary to confirm that the process was performed. The first FSM send a signal (start do it) and the second one initialize the process change its state.

    Could anyone recommend me a paper, text, tutorial, book or something with explanation about how design a similar logic or perhaps you can give me an example . Maybe if a had an example I find out what it's wrong with my design.

    Sorry for anything,

    higor
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Or if you post your design, we could tell you what's wrong with it. But I don't know if it's something sensitive. You can also use Quartus to show you in the code or in the RTL where those gated clocks are coming from.

    Is your code written in Verilog HDL or VHDL? I'm assuming it is HDL of some kind.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    General suggestions:

    * Read up on clock enables.

    *Register inputs and outputs if at all possible; while this often complicates the timeing and might add slight delays, that's what simulation is for.

    *Do each state machine as independently as possible in simulation and test and verify it works to the best of your early anticipation of how it should work

    * Stick to one clock unless you really really have to make a new clock domain. This is usually an acceptable Use case unless you have external logic or DSP that requires specific rates. If you do have to do new domains, read up on fifo's and single signal metastability; they are essential if you are running more than one clock domain.

    * Synchronize all incoming signals and data. Note you have to use some fifo like mechanism if your inputs are asynchronous to the clock that is used to latch them.

    I hope that helps. It's just some general advice if you are very new to the fpga world.