Ripple clock caused by State Machines

Thank you guys,

I'm getting started with design and I have much much more to learn. I just want to clarify:

Jake:

Do you recommend to put a register between each Layer? If yes, this register wold be tigered by a global clock and to the input D should be assigned a signal come from the state machine?

Tricky:

How could I use those states to enable the others logic parts? each machine, it is supposed to be independent in one way. For example: If a data arrives to layer one, so it is processed and then forward to layer two. At this moment the layer one could receive others data to be processed.

As I told you, I'm just learning yet. Please, be more clear.

Thank you very much guys,

Higor