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Altera_Forum
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16 years ago

Ripple clock caused by State Machines

Hi, I'm trying to make a project, so I have 6 state machines which are related/cascaded. I have 3 state machines layers and a clock flow over those state machines as follows: Layer 1: FSM...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Or if you post your design, we could tell you what's wrong with it. But I don't know if it's something sensitive. You can also use Quartus to show you in the code or in the RTL where those gated clocks are coming from.

Is your code written in Verilog HDL or VHDL? I'm assuming it is HDL of some kind.

Jake