Ripple clock caused by State Machines

Ok People,

I really understand what you told me. I'm using just one clock for all those state machines. I'm not dividing or multiplying it. The design looks ok to me, I can't to figure out what it's happen to make that warning appears.

Jake, my logic don't needs a "done" signal back. It's not necessary to confirm that the process was performed. The first FSM send a signal (start do it) and the second one initialize the process change its state.

Could anyone recommend me a paper, text, tutorial, book or something with explanation about how design a similar logic or perhaps you can give me an example . Maybe if a had an example I find out what it's wrong with my design.

Sorry for anything,

higor