Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Ripple clock caused by State Machines

Hi, I'm trying to make a project, so I have 6 state machines which are related/cascaded. I have 3 state machines layers and a clock flow over those state machines as follows: Layer 1: FSM...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

As already said, hierarchical state machines are supposed to use a single system clock and clock enables rather than gated clocks for conditional activation of a particular state machine.

Because the whole design is located in a single clock domain, state variables from one state machine can be directly processed in an other one, normally.