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Altera_Forum
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16 years ago

Ripple clock caused by State Machines

Hi, I'm trying to make a project, so I have 6 state machines which are related/cascaded. I have 3 state machines layers and a clock flow over those state machines as follows: Layer 1: FSM...
Altera_Forum's avatar
Altera_Forum
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16 years ago

It is normally bad practice, and bad design, to use logic to drive internal clocks inside FPGAs. It is normally much much better and much easier to debug if you use a common clock for all logic, and then use the logic to generate enable signals for other parts of the design.

I would recommend that you use the states, and not a ripple clock, to enable the other parts of the logic.