Ripple clock caused by State Machines

General suggestions:

* Read up on clock enables.

*Register inputs and outputs if at all possible; while this often complicates the timeing and might add slight delays, that's what simulation is for.

*Do each state machine as independently as possible in simulation and test and verify it works to the best of your early anticipation of how it should work

* Stick to one clock unless you really really have to make a new clock domain. This is usually an acceptable Use case unless you have external logic or DSP that requires specific rates. If you do have to do new domains, read up on fifo's and single signal metastability; they are essential if you are running more than one clock domain.

* Synchronize all incoming signals and data. Note you have to use some fifo like mechanism if your inputs are asynchronous to the clock that is used to latch them.

I hope that helps. It's just some general advice if you are very new to the fpga world.