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Altera_Forum's avatar
Altera_Forum
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16 years ago

Ripple clock caused by State Machines

Hi, I'm trying to make a project, so I have 6 state machines which are related/cascaded. I have 3 state machines layers and a clock flow over those state machines as follows: Layer 1: FSM...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The answer lies in your code. Those signals you've indicated must be connected as clocks to at least one register in your design. Maybe it's intentional, maybe not.

Jake