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zjj's avatar
zjj
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20 hours ago

retiming issue

we develop a project with agilex7 fpga and using quartus pro 25.3 version.

now we fix timing by analyze the retiming report.  we see the following retiming restriction:

But the register  GEN_REG_INUT.R_DATA[0][0]  is directly driven by quartus hyper register, and it has no power up value and no sync reset. 

the retiming critical path as follow:

-------------------------------------------+

; Critical Chain Details ;

+--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Path Info ; Register ; Register ID ; Element ;

+--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Power-up Restriction ; ALM Register ; #1 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0] ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]|q ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X221_Y195_N0_I99 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~R1_X221_Y195_N0_I10 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~C4_X220_Y191_N0_I11 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LOCAL_INTERCONNECT_X220_Y191_N0_I26 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~BLOCK_INPUT_MUX_PASSTHROUGH_X220_Y191_N0_I35 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X220_Y191_N0_I39 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|dataf ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|combout ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~cw_la_lab/lab_lut6outt[4] ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X220_Y191_N0_I138 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X220_Y190_N0_I17 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X220_Y190_N0_I16 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X208_Y190_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X196_Y190_N0_I2 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y182_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X184_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X172_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X160_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X148_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X136_Y174_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y166_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y158_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y150_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y142_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y134_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X124_Y134_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y126_N0_I0 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y118_N0_I0 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R0_X123_Y118_N0_I2 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R2_X124_Y118_N0_I15 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X126_Y118_N0_I31 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y118_N0_I30 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y119_N0_I30 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LOCAL_INTERCONNECT_X126_Y120_N0_I61 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_BLOCK_INPUT_MUX_PASSTHROUGH_X126_Y120_N0_I80 ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X126_Y120_N0_I82 ;

; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|pack_data_padding_cross~xtophalf/xale2/xcw_ml_le_regctrl/xcw_la_le_regctrl_reg/sclr_out ;

; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4]|sclr ;

Long Path (Critical) ; ALM Register ; #2 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4] ;

 

 

why  quartus report the retiming restriction?

Compilation
Timing

1 Reply

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 hours ago

    Is the path failing timing?  There will always be a critical chain that can no longer be retimed in each clock domain in the design.  

    If you are still failing timing in the design, instead try a fast forward compilation to get pinpoint recommendations for what you could change in the design to overcome any retiming restrictions that may contribute to timing failing.