Forum Discussion
Occasional Contributorretiming issue
Super ContributorIs the path failing timing? There will always be a critical chain that can no longer be retimed in each clock domain in the design.
If you are still failing timing in the design, instead try a fast forward compilation to get pinpoint recommendations for what you could change in the design to overcome any retiming restrictions that may contribute to timing failing.
zjjI also see the fast forward compilation report as below:
it still report the power-up state of the register in the scfifo. the fifo is quartus ip, I doesn't know to change power-up state of the register to DON't care.
- KennyT_altera
Is there any update for the above request?
- zjj
in the retiming.rpt and fastfoward.rpt, I also see the altera scfifo ip shows power-up restriction as below:
how to fix the retiming restriction?
