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zjj's avatar
zjj
Icon for New Contributor rankNew Contributor
22 hours ago

retiming issue

we develop a project with agilex7 fpga and using quartus pro 25.3 version. now we fix timing by analyze the retiming report.  we see the following retiming restriction: But the register  GEN_RE...
Compilation
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 hours ago

Is the path failing timing?  There will always be a critical chain that can no longer be retimed in each clock domain in the design.  

If you are still failing timing in the design, instead try a fast forward compilation to get pinpoint recommendations for what you could change in the design to overcome any retiming restrictions that may contribute to timing failing.