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zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

retiming issue

we develop a project with agilex7 fpga and using quartus pro 25.3 version. now we fix timing by analyze the retiming report.  we see the following retiming restriction: But the register  GEN_RE...
Compilation
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 month ago

Is the path failing timing?  There will always be a critical chain that can no longer be retimed in each clock domain in the design.  

If you are still failing timing in the design, instead try a fast forward compilation to get pinpoint recommendations for what you could change in the design to overcome any retiming restrictions that may contribute to timing failing.

zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

I also see the fast forward compilation report as below:

it still report the power-up state of the register in the scfifo. the fifo is quartus ip, I doesn't know to change  power-up state of the register to DON't care.

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Is there any update for the above request?

    • zjj's avatar
      zjj
      Icon for Occasional Contributor rankOccasional Contributor
      1 month ago

      in the retiming.rpt and fastfoward.rpt,  I also see the altera scfifo ip shows power-up restriction as below:

      how to fix the retiming restriction?

      • KennyT_altera's avatar
        KennyT_altera
        Icon for Super Contributor rankSuper Contributor
        1 month ago

        Hi,

         

        Regarding the power-up restriction reported for altera_scfifo in retiming.rpt / fastforward.rpt, this is not generally something that can be resolved by forcing the tool to ignore the power-up condition.

        For RAM/DSP retiming, retiming is only supported when:

        • the RAM/DSP is in a supported mode
        • the pipelining FFs before the RAM/DSP have power-up don’t care for forward retiming
        • the pipelining FFs after the RAM/DSP have power-up don’t care for backward retiming

        There are also RAM configurations that are not retimed, such as:

        • RAMs with memory initialization
        • mixed-width RAMs
        • RAMs with forwarding mode enabled

        For altera_scfifo, the restriction is typically more limiting than for a simple RAM, because the FIFO contains internal state and startup behavior beyond a plain memory array. Because of that, even if the report shows a power-up restriction, there may not be a safe or supported method to force retiming through the FIFO.

        The recommended guidance is:

        • do not try to override the power-up restriction
        • treat the FIFO as a retiming boundary
        • improve timing by adding explicit pipeline stages around the FIFO
        • where applicable, use FIFO configuration options that help timing

        In short, the restriction exists to preserve functional correctness, and bypassing it is not recommended.

         

        I will attached a simple design show how retiming works for the RAM, kindly check your inbox on this.

         

        Thanks,

        Best regards,
        Kenny Tan