ContributorHi,
Pay attention to leave the REMOVE_REDUNDANT_LOGIC_CELLS option to ON if you are using a reconfig pll [at least in stratix 3 FPGA].
Turning the option OFF makes 3 redundant cells not removed and the PLL fails to produce aproper clock after reconfiguration.
File is altpll_reconfig_quartus.vhd,
SIGNAL cuda_combout_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
--Quartus VERSION 13.1
Super ContributorHi,
Can you circle out the different base on your screenshot?
I will try it on Q18.1 to see if the problem still exist.
Thanks,
ContributorHi,
Please see the diff in the new attachment.
ContributorPlease note that timings are meet for setup and hold in both scenario's,
so this is not timing related (slack of +0.3 ns).
If you need the qar to reproduce it, let me know (give me your personal placeholder as I cannot give it on the forum).
Please note that I will stick to v13.1 (last supported version for the stratix III fpga).
Super ContributorHi,
I had send you a separate mail for the qar. you may check your inbox
Thanks,
Best regards,
ContributorSo, what is the outcome KTan9?
Is the issue still present?
Super ContributorHi,
Sorry, I had been quite busy. I will test it by today.
Thanks
Super ContributorHi,
Given that this bugs is in the older version of Quartus Prime, this bug/issue is currently in the lower priority list for Intel to fix. We apologize for any inconvenience.
Thanks
ContributorI removed manually in the RTL code the lines cuda_combout_wire as sometime quartus was still not removing them for some reason.
Now it works fine.
ContributorI'm re-using this code again and faced the same issue (of course),
but as I wanted to use that option globally to preserve the netlist from Synplify and preserve my clock nets name point,
I'm now using this in the .qsf:
#No global optimization
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS OFF
#But this is required otherwise the variable PLL clock is not working
set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON -to "adjustable_pll:adjustable_pll_inst"
