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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
7 years ago

REMOVE_REDUNDANT_LOGIC_CELLS is important, take care.

Hi, Pay attention to leave the REMOVE_REDUNDANT_LOGIC_CELLS option to ON if you are using a reconfig pll [at least in stratix 3 FPGA]. Turning the option OFF makes 3 redundant cells not removed and...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago

Hi,

Can you circle out the different base on your screenshot?

I will try it on Q18.1 to see if the problem still exist.

Thanks,

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