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AEsqu's avatar
AEsqu
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7 years ago

REMOVE_REDUNDANT_LOGIC_CELLS is important, take care.

Hi, Pay attention to leave the REMOVE_REDUNDANT_LOGIC_CELLS option to ON if you are using a reconfig pll [at least in stratix 3 FPGA]. Turning the option OFF makes 3 redundant cells not removed and...
AEsqu's avatar
AEsqu
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7 years ago

Please note that timings are meet for setup and hold in both scenario's,

so this is not timing related (slack of +0.3 ns).

If you need the qar to reproduce it, let me know (give me your personal placeholder as I cannot give it on the forum).

Please note that I will stick to v13.1 (last supported version for the stratix III fpga).