Hi, Is in VHDL something similar to overriding a function or giving function as parameter to an entity (similar to c++ or javascript). I'm implementing some image processing components which are similar to each other up to one or two functions which I use to calculate pixel values. I want to create one entitiy and provide different functions as parameters to this entity. I can't export signals and compute values outside of entity because function is used inside in several places, in for loops etc. What is the best way to implement this? My current idea is to create a large main function which calls other small functions according to parameter given to entity. The entity always calls the main function and gives a selection parameter.

You cant give a function to an entity. It just exists as a function that you can call wherever it has scope. But from the sounds of your question you're a software programmer, and your hardware architecture sounds like a software program. This will yield terrible results in an FPGA if it even works at all. My Advise - start again, and draw your circuit (not functions) on a peice of paper outlining where all the things like memories, state machines etc are in your processing pipeline.

Am I right ? for those who good at software - any HDL similar to assembler. function or procedure similar to macros. what in FPGA design called assembler phase similar to writing pure machine code. So any question about overloading function should be rejected. It is good answer who not familar with HDL.

--- Quote Start --- Am I right ? for those who good at software - any HDL similar to assembler. function or procedure similar to macros. what in FPGA design called assembler phase similar to writing pure machine code. So any question about overloading function should be rejected. It is good answer who not familar with HDL. --- Quote End --- I would NOT say HDL is similar to assembler. Thats only the case if you write very structural HDL (individual gates and registers). You can write some fairly abstract HDL that will work very well in the synthesisor. Functions and procedures are perfectly fine to use in your HDL - but only if you understand the circuit you're trying to describe.

:) stupid question but may be VHDL close to LISP?! in any case you have code like out <= func(in1, in2, ...) or proc(in1, in2, inout1, inout2, out1, out2, ...) and you can have a lot of similar expression that evaluated in parallel. there is side effect of function or procedure call - hardware will be generated.

No, VHDL and Verilog are not at all like software. They are totally different. There is much confusion because the languages resemble software but these are not software. Think of modules/packages as your custom made ICs. instantiating a module is like placing an IC on a board. The ports are the wires. You need to think in terms of everything running in parallel, state machines and logic equations. Thinking in terms of objects, function calls a loops will lead you astray. This is electronics design, not implementing software with hardware. My advice, as a software guy who got into this as a hobby is to ignore everything about software design because this is not software.

Question about good design: overriding functions, function parameters or similar

11 Replies

Altera_Forum
Honored Contributor
11 years ago
You cant give a function to an entity. It just exists as a function that you can call wherever it has scope.

But from the sounds of your question you're a software programmer, and your hardware architecture sounds like a software program. This will yield terrible results in an FPGA if it even works at all.

My Advise - start again, and draw your circuit (not functions) on a peice of paper outlining where all the things like memories, state machines etc are in your processing pipeline.
Altera_Forum
Honored Contributor
11 years ago
Am I right ?
for those who good at software -
any HDL similar to assembler.
function or procedure similar to macros.
what in FPGA design called assembler phase similar to writing pure machine code.

So any question about overloading function should be rejected. It is good answer who not familar with HDL.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Am I right ?
for those who good at software -
any HDL similar to assembler.
function or procedure similar to macros.
what in FPGA design called assembler phase similar to writing pure machine code.

So any question about overloading function should be rejected. It is good answer who not familar with HDL.
--- Quote End ---

I would NOT say HDL is similar to assembler. Thats only the case if you write very structural HDL (individual gates and registers). You can write some fairly abstract HDL that will work very well in the synthesisor.
Functions and procedures are perfectly fine to use in your HDL - but only if you understand the circuit you're trying to describe.
Altera_Forum
Honored Contributor
11 years ago
:) stupid question but may be VHDL close to LISP?!
in any case you have code like out <= func(in1, in2, ...) or proc(in1, in2, inout1, inout2, out1, out2, ...)
and you can have a lot of similar expression that evaluated in parallel.
there is side effect of function or procedure call - hardware will be generated.
Altera_Forum
Honored Contributor
11 years ago
No, VHDL and Verilog are not at all like software. They are totally different. There is much confusion because the languages resemble software but these are not software. Think of modules/packages as your custom made ICs. instantiating a module is like placing an IC on a board. The ports are the wires. You need to think in terms of everything running in parallel, state machines and logic equations. Thinking in terms of objects, function calls a loops will lead you astray. This is electronics design, not implementing software with hardware. My advice, as a software guy who got into this as a hobby is to ignore everything about software design because this is not software.
Altera_Forum
Honored Contributor
11 years ago
I've indeed started as software programmer 20 years ago. But since couple of years I'm also doing VHDL for an commercial product. I completely agree that VHDL is not like any of pure software languages because of different paradigm. But the idea of reusing code is something fundamental and belongs to good style for both worlds. Actually I want to do exactly this: "giving function to an entity". If VHDL doesn't have such features I would even consider code generation technics for this but I hope to find a solution with VHDL only. Perphaps SystemC wrapper could do this also.
Altera_Forum
Honored Contributor
11 years ago
You havent been very clear. I think you are using the term function (which is a VHDL keyword) to mean functionality.
Entities can be given generics which are constants, but can be set during module instantiation (design elaboration phase). These can be used to completly change the functionality of any entity, usually using generate statements. Generates act at elaboration time.

You can use generics anywhere inside the code.
Re-useable code often uses generics to make a module parameterisable.
Altera_Forum
Honored Contributor
11 years ago
Maybe one search for packages for VHDL code reuse?!
But yes, entity is just declaration for black-box and can contain several generics (compare with# define in C) and port decalrations: inputs and outputs, and it is used for hardware description. entity is not similar to C++ class at all.
you can create package for many function as you wish but formal arguments mostly are variables. Be careful with VHDL procedure and function when they use signals.
Altera_Forum
Honored Contributor
11 years ago
I put reusable code into VHDL functions and reuse them in processes. I understand how to provide different architectures for entities implementation and entity configuration concepts. The generate statement is not of big use because function defintion itself is actually not synthesised to anything as long as it's not used inside a process or signal assignment or similar. Actually something similar to configurations but for functions is what would help. e.g. You define function interface in the entity and can provide function implementation from outside similar to configuration of entities.
I will go with a global function and a generic parameter in enitity which selects what function is actually has to calculate. Thanks for input.
Altera_Forum
Honored Contributor
11 years ago
I would be wary about putting too much functionality into functions. Functions cannot be pipelined, so if you need the extra registers to break up a function, you will have to separate the code into two functions - not very reusable.

VHDL 2008 introduced the ability to put generics on packages and declare generic types and functions on anything. But I dont think this will be supported by the synth vendors any time soon (its supported by sim tools).

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Question about good design: overriding functions, function parameters or similar

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