Question about good design: overriding functions, function parameters or similar

I put reusable code into VHDL functions and reuse them in processes. I understand how to provide different architectures for entities implementation and entity configuration concepts. The generate statement is not of big use because function defintion itself is actually not synthesised to anything as long as it's not used inside a process or signal assignment or similar. Actually something similar to configurations but for functions is what would help. e.g. You define function interface in the entity and can provide function implementation from outside similar to configuration of entities.