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Altera_Forum's avatar
Altera_Forum
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10 years ago

Question about good design: overriding functions, function parameters or similar

Hi, Is in VHDL something similar to overriding a function or giving function as parameter to an entity (similar to c++ or javascript). I'm implementing some image processing components which...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

:) stupid question but may be VHDL close to LISP?!

in any case you have code like out <= func(in1, in2, ...) or proc(in1, in2, inout1, inout2, out1, out2, ...)

and you can have a lot of similar expression that evaluated in parallel.

there is side effect of function or procedure call - hardware will be generated.