Clock domain crossing?

I two vectors crossing from 150MHz-domain to 120MHz-domain, and the design assistant lists violations according to rule D101.

I do not understand why only valid-bits for some of the channels get these violations. And, why the data-buses seems to be fine.

The vectors are actually 16 channels of data/valid busses. Every channel is prolonged to a 2x clock in the 150MHz domain, and then synchronized through dual FFs in the 120MHz domain.

I have tried forcing Quartus by adding these global assignments

I have also added these attributes in my source code.

The technology-viewer still shows a LOGIC_CELL_COMB between *_s1[0].tvalid and *_s2[0].tvalid, shouldn't there be a direct connection between the two FFs?

I am stuck understanding why this occurs. Any suggestions on what can be done?