Question about good design: overriding functions, function parameters or similar

Maybe one search for packages for VHDL code reuse?!

But yes, entity is just declaration for black-box and can contain several generics (compare with# define in C) and port decalrations: inputs and outputs, and it is used for hardware description. entity is not similar to C++ class at all.

you can create package for many function as you wish but formal arguments mostly are variables. Be careful with VHDL procedure and function when they use signals.