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Altera_Forum's avatar
Altera_Forum
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10 years ago

Question about good design: overriding functions, function parameters or similar

Hi, Is in VHDL something similar to overriding a function or giving function as parameter to an entity (similar to c++ or javascript). I'm implementing some image processing components which...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Maybe one search for packages for VHDL code reuse?!

But yes, entity is just declaration for black-box and can contain several generics (compare with# define in C) and port decalrations: inputs and outputs, and it is used for hardware description. entity is not similar to C++ class at all.

you can create package for many function as you wish but formal arguments mostly are variables. Be careful with VHDL procedure and function when they use signals.