Question about good design: overriding functions, function parameters or similar

No, VHDL and Verilog are not at all like software. They are totally different. There is much confusion because the languages resemble software but these are not software. Think of modules/packages as your custom made ICs. instantiating a module is like placing an IC on a board. The ports are the wires. You need to think in terms of everything running in parallel, state machines and logic equations. Thinking in terms of objects, function calls a loops will lead you astray. This is electronics design, not implementing software with hardware. My advice, as a software guy who got into this as a hobby is to ignore everything about software design because this is not software.