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Altera_Forum's avatar
Altera_Forum
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10 years ago

Question about good design: overriding functions, function parameters or similar

Hi, Is in VHDL something similar to overriding a function or giving function as parameter to an entity (similar to c++ or javascript). I'm implementing some image processing components which...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Am I right ?

for those who good at software -

any HDL similar to assembler.

function or procedure similar to macros.

what in FPGA design called assembler phase similar to writing pure machine code.

So any question about overloading function should be rejected. It is good answer who not familar with HDL.