Question about good design: overriding functions, function parameters or similar

I've indeed started as software programmer 20 years ago. But since couple of years I'm also doing VHDL for an commercial product. I completely agree that VHDL is not like any of pure software languages because of different paradigm. But the idea of reusing code is something fundamental and belongs to good style for both worlds. Actually I want to do exactly this: "giving function to an entity". If VHDL doesn't have such features I would even consider code generation technics for this but I hope to find a solution with VHDL only. Perphaps SystemC wrapper could do this also.