New ContributorQuartus synthesis deletes bits of a variable that gets a constant value
Hi
I am running synthesis on a module that has to reg variables of [11:0] bits.
These variables are getting constant values according to a switch case on two of the inputs.
This is my code:
module HT3Input12 (
input selector_msb,
input selector_lsb,
input [11:0] InData0,
input [11:0] InData1,
output check
);
wire [11:0] Data0 = InData0;
wire [11:0] Data1 = InData1;
reg [11:0] Compare_data0A0;
reg [11:0] Compare_data1A1;
//assign Compare = ( reset_n == 1'b1 ) ? 12'hFFF : 12'd0 ;
//-------------------------------------------------------
// Selectors MAP
//-------------------------------------------------------
// 00 - Send 0s on all pins
// 01 - Send a series of '101010...' , first bit is '1'
// 10 - Send a series of '010101...' , first bit is '0'
// 11 - Send 1s on all pins
//-------------------------------------------------------
always @(*)
case ({selector_msb,selector_lsb})
2'b00:
begin
Compare_data0A0 <= 12'd0;
Compare_data1A1 <= 12'd0;
end
2'b01:
begin
Compare_data0A0 <= 12'hABC;
Compare_data1A1 <= 12'h789;
end
2'b10:
begin
Compare_data0A0 <= 12'b101010101010;
Compare_data1A1 <= 12'b101010101010;
end
2'b11:
begin
Compare_data0A0 <= 12'hFFF;
Compare_data1A1 <=12'hFFF;
end
endcase
//assign Compare = ( selector_msb == 1'b1 ) ? 12'hFFF : 12'd0 ;
assign check = ((Data0 == Compare_data0A0) && (Data1 == Compare_data1A1)) ? 1'b1 : 1'b0 ;
In synthesis - there is only one of the two regs left (only Compare_data0A0) and it has only 2 bits instead of 12. It can also be seen in the SignalTap pre-synthesis signals and Schematics - the 9 LSB are deleted.
Can you explain why this is happening?
When I declare them both as output reg - problem solved and they're both declared as expected after synthesis.
In my .v file you can see Compare_data0A0 and Compare_data1A1 that are assigned in the case and in synthesis most of their bits are gone.
the path to the .v file in the zip file that I attached is: for_check/DIE1/HT3Input12.v
The input patterns requested all match to 4 possible cases – the MSB exactly, the LSB exactly, Or values E or 8
This seems to match exactly to the design being inferred by synthesis – what is being compared is ambiguous in the netlist viewer diagram, but it is using the MSB, LSB and these two 4-bit constants to accomplish the comparison.
Since every individual bit takes resources in an FPGA, it makes sense to minimize the functions like this to save resources.
