Quartus synthesis deletes bits of a variable that gets a constant value

It can be seen in Signal Tap tool:
You can see here that compare_data0 has only 2 bits, and compare_data1 is not even there.

And also in scheme it can be seen that the constant that goes to comparison is incorrect:

In the lab on the FPGA itself it does not compare it correctly. I get 0x800 or 0xC00 for the constants which means only the two MSBs are changing.

I am adding here again the code:

//---------------------------------------------------------------------------------------------------
module HT3Input12 (
input selector_msb,
input selector_lsb,
input [11:0] InData0,
input [11:0] InData1,
output check
);

wire [11:0] Data0 = InData0;
wire [11:0] Data1 = InData1;

reg [11:0] Compare_data0;
reg [11:0] Compare_data1;

//-------------------------------------------------------
// Selectors MAP
//-------------------------------------------------------
// 00 - Send 0s on all pins
// 01 - Send a series of '101010...' , first bit is '1'
// 10 - Send a series of '010101...' , first bit is '0'
// 11 - Send 1s on all pins
//-------------------------------------------------------

always @(*)
case ({selector_msb,selector_lsb})
2'b00:
begin
Compare_data0 = 12'd0;
Compare_data1 = 12'd0;
end
2'b01:
begin
Compare_data0 = 12'hABC;
Compare_data1 = 12'h789;
end
2'b10:
begin
Compare_data0 = 12'b101010101010;
Compare_data1 = 12'b101010101010;
end
2'b11:
begin
Compare_data0 = 12'hFFF;
Compare_data1 =12'hFFF;
end
endcase

assign check = ((Data0 == Compare_data0) && (Data1 == Compare_data1)) ? 1'b1 : 1'b0 ;

endmodule

//---------------------------------------------------------------------------------------------------

Do you know how can I report a bug on Quartos?