
module HT3Input12 (
    input           selector_msb,
	input           selector_lsb,
	input   [11:0]  InData0,
	input   [11:0]  InData1,
   output          check, //Outputs to LED
	output reg [11:0] Compare_data0,
   output reg [11:0] Compare_data1         
);

wire [11:0] Data0 = InData0;
wire [11:0] Data1 = InData1;

reg [11:0] Compare_data0A0;
reg [11:0] Compare_data1A1;

//assign Compare = ( reset_n == 1'b1 ) ? 12'hFFF : 12'd0 ;

//-------------------------------------------------------
//                  Selectors MAP
//-------------------------------------------------------
//  00 - Send 0s on all pins
//  01 - Send a series of '101010...' , first bit is '1'
//  10 - Send a series of '010101...' , first bit is '0'
//  11 - Send 1s on all pins
//-------------------------------------------------------


    always @(*)
        case ({selector_msb,selector_lsb})
            2'b00:
				begin
            Compare_data0A0 <= 12'd0;
            Compare_data1A1 <= 12'd0;
				end
				2'b01:
				begin
				Compare_data0A0 <= 12'hABC;
				Compare_data1A1 <= 12'h789;
				end
				2'b10:
				begin
				Compare_data0A0 <=  12'b101010101010;
				Compare_data1A1 <= 12'b101010101010;
				end
				2'b11:
            begin
            Compare_data0A0 <= 12'hFFF;	
            Compare_data1A1 <=12'hFFF;
            end
          
    endcase

//assign Compare = (  selector_msb == 1'b1 ) ? 12'hFFF : 12'd0 ;

assign check = ((Data0 == Compare_data0A0) && (Data1 == Compare_data1A1)) ? 1'b1 : 1'b0 ;

//wire [11:0] eq;
//assign eq = ( checkslec == 1'b1 ) ? 12'hAAA :  ;
/*
reg [10:0 ] In0;
reg [10:0 ] In1;

reg [10:0 ] In0_d;
reg [10:0 ] In1_d;

reg [10:0 ] In0_dd;
reg [10:0 ] In1_dd;

reg [ 10:0 ] data0;
reg [ 10:0 ] data1;


always @( posedge clk0 or negedge reset_n )
begin
	if (~reset_n)
	    begin
		In0    <= 11'd0;
		In0_d  <= 11'd0;
        In0_dd <= 11'd0;
		data0  <= 11'd0;
	    end
	else
	    begin
		In0    <= InData0;
		In0_d  <= In0;
		In0_dd <= In0_d;
		if ( (~In0_dd [10] ) && In0_d [10] )	//raising edge
		    begin
			data0 <= In0_d [10:0];
	    	end
    	end
end

always @( posedge clk1 or negedge reset_n )
begin
	if (~reset_n)
    	begin
		In1    <= 11'd0;
		In1_d  <= 11'd0;
        In1_dd <= 11'd0;
		data1  <= 11'd0;
    	end
	else
    	begin
		In1    <= InData1;
		In1_d  <= In1;
		In1_dd <= In1_d;
		if ( (~In1_dd [10] ) && In1_d [10] )	//raising edge
	    	begin
			data1 <= In1_d [10:0];
	    	end
    	end
end


assign check = ( (data0 == 11'h7FF) && (data1 == 11'h7FF) ) ? 1'b1 : 1'b0 ;
*/







endmodule
