Forum Discussion
New ContributorQuartus synthesis deletes bits of a variable that gets a constant value
The input patterns requested all match to 4 possible cases – the MSB exactly, the LSB exactly, Or values E or 8
This seems to match exactly to the design being inferred by synthesis – what is being compared is ambiguous in the netlist viewer diagram, but it is using the MSB, LSB and these two 4-bit constants to accomplish the comparison.
Since every individual bit takes resources in an FPGA, it makes sense to minimize the functions like this to save resources.
Regular ContributorI respectfully disagree. What I explained is the correct behavior that that Quartus optimization should show. Constant logic is evaluated and replaced by constants. That is normal behavior. If an output is not used, it can be pruned back until all logic basically disappears as Quartus detects and keeps removing unused logic. This is the default optimization behavior. You can override it with synthesis directives as I explained.
Now the allegation that you say Quartus is incorrectly replacing the constant logic with incorrect constants is another issue. It could certainly be that you uncovered a bug in Quartus.
But in your test check.zip code there are multiple instances of your module, and each instance will be optimized differently. So my suspicion is you think you are looking a the optimized version of instance A when you are really looking at the optimized version of instance B (or C or D).
Just my guess at this point. Your test code is way to big for me to go thru. You need to make a smaller test example to exhibit the issue.
NitzanDI tried to make it smaller now, having only one .v file - Is it something that you can look at now?
