Forum Discussion

NitzanD's avatar
NitzanD
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Quartus synthesis deletes bits of a variable that gets a constant value

Hi 🙂 I am running synthesis on a module that has to reg variables of [11:0] bits. These variables are getting constant values according to a switch case on two of the inputs. This is my code: ...
  • JDP's avatar
    JDP
    5 years ago

    The input patterns requested all match to 4 possible cases – the MSB exactly, the LSB exactly, Or values E or 8

    This seems to match exactly to the design being inferred by synthesis – what is being compared is ambiguous in the netlist viewer diagram, but it is using the MSB, LSB and these two 4-bit constants to accomplish the comparison.

    Since every individual bit takes resources in an FPGA, it makes sense to minimize the functions like this to save resources.

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
5 years ago

Simply, Quartus synthesis optimization is 'smart'. It will reduce logic to make it simpler. It will detect logic that is constant and eliminate it, and replace it with the constant value. So that is what is going on.

This optimization is a feature and not a bug.

If you really want to preserve the (constant) register bits, you need to forcefully tell Quartus to do so, making the registers outputs, or using some of the attributes you can apply to signals and registers. Like 'syn_preserve':

See: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_preserve.htm

  • NitzanD's avatar
    NitzanD
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks for your answer !
    I tried the syntax in the link that you added but it only kept several bits and not all of them, but I will check if it remains correct and update.
    What you are explaining is wrong in my opinion because its not an optimization - its a bug. it creates a different constant which makes it a bug in the code.