Forum Discussion

NitzanD's avatar
NitzanD
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Quartus synthesis deletes bits of a variable that gets a constant value

Hi 🙂 I am running synthesis on a module that has to reg variables of [11:0] bits. These variables are getting constant values according to a switch case on two of the inputs. This is my code: ...
  • JDP's avatar
    JDP
    5 years ago

    The input patterns requested all match to 4 possible cases – the MSB exactly, the LSB exactly, Or values E or 8

    This seems to match exactly to the design being inferred by synthesis – what is being compared is ambiguous in the netlist viewer diagram, but it is using the MSB, LSB and these two 4-bit constants to accomplish the comparison.

    Since every individual bit takes resources in an FPGA, it makes sense to minimize the functions like this to save resources.

JDP's avatar
JDP
Icon for New Contributor rankNew Contributor
5 years ago

The input patterns requested all match to 4 possible cases – the MSB exactly, the LSB exactly, Or values E or 8

This seems to match exactly to the design being inferred by synthesis – what is being compared is ambiguous in the netlist viewer diagram, but it is using the MSB, LSB and these two 4-bit constants to accomplish the comparison.

Since every individual bit takes resources in an FPGA, it makes sense to minimize the functions like this to save resources.