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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all,

I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so real used space is 81% of ALM.

Compilation fail due to

Warning (16618): Fitter routing phase terminated due to routing congestion. Congestion details can be found in Chip Planner.

Critical Warning (188026): The Fitter failed to successfully route the design. You may be able get this design to route by making design modifications, changing the fitter seed or by enabling the Fitter Aggressive Routability Optimizations logic option.

etc..

Attached a Chip Planner blank and with congestion map. Threshold is at 99%, why in black area (= no my logic) there is a congestion? What is in that area (circled yellow into images)?

I am trying to change some settings and floorplanning design but every compilation take 1+ hour (I use .vqm file generated by another tool so analysis and synthesis is fast, i do just routing)

Image link: http://it.tinypic.com/r/2wecbdk/9

Thank you

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    That sounds highly inefficient. Can't you insert data during run time? What latency is required? If you don't care about latency then you could re use as much logic s you wanted.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    This isn't real-time data processing, problem is one-shoot but resolution is very long so need to use parallel computation

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If you have as long as you like, then make the calculation use time division multiplex. eg. use one multipler to calculate 8 different values in 8 clocks rather than 8 multipliers to get the value in 1 clock. Stuff like that. Then all you worry about is getting data in and out of ram. The fan out is really small and the routing is simpler.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Nobody else asked so I will. Any chance you can move to a larger device, like an Arria V? Or split the design into two C5s? Stuffing a device to 99% full can be a costly endeavor. Even if you spend the NRE now to squeeze it in, if you ever need to add logic or even fix a bug, you could be in trouble. And with the device that full using SignalTap is impossible. Even if you verify everything in simulation, SignalTap can still be a lifesaver when unexpected things happen in hardware.

    I got stuck in this situation once in an Arria II device (99% full) because system requirements changed over time. For a while we got away with it. Then over time a couple of changes were made and it started to fail timing, so I had to slow down the memory clock. Then eventually it just would no longer fit. The extra cost of using a larger device to start with would have been a huge cost savings in the end. And we eventually ended up there anyway.

    If this is just a prototype or hobby project then have at it and good luck. But going into production with that part 99% full would be extremely risky.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I don't have as long as I want, it is on FPGA to speed up so I try to get max performance :)

    Clearly one day this will go into Stratix/Arria devices OR multiple Cyclone devices but I want to close a demo with just a Cyclone V for demonstration. I don't use 99% but 81% that seem reasonable. Then 14% of ALM are unavailable due to congestion :(

    By design routing "should" be simple but when divisors (100+) are synthetized with Synplify with pipeline inferred with retiming problem arise.. (12+ hours of RTL compilation + Fitter that fail after 1+ hour).. too things packed.. I have to try to use LPM_DIV with pipeline but this isn't a great option for "portability" of system.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    12 hours of RTL compilation? That seems way, way too long. Can you do partitions(I think they have another name for it) in Synplify to reduce that?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes, but first time it compile all partitions. I noticed that compiling same design for Spartan6 LX150 is better for compile time (2h+ for RTL).. maybe Synplify is more optimized for Xilinx architecture.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    ... but when divisors (100+) are synthetized ...

    --- Quote End ---

    Wow, 100+ dividers! There could be room for improvement? Are all numerators truly dynamic, or are some loaded by the application, or are some constant?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Dividers (fixed point) are always 1/X where X change so no tricks..

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Why are you doing 1/X divides? are the results of this fed into a multiplier? why not just do Y/X in the first instance?

    12+ hours of RTL compile is far far far too long. The longest Ive ever seen (for a very full stratix 4) was 1 hour (with 4-8 hours fit). Do you have some rams that are actually being synthesised as registers? that is usually the culprit for long synthesis (and would then result in a very full and congested chip).