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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If you have as long as you like, then make the calculation use time division multiplex. eg. use one multipler to calculate 8 different values in 8 clocks rather than 8 multipliers to get the value in 1 clock. Stuff like that. Then all you worry about is getting data in and out of ram. The fan out is really small and the routing is simpler.