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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Why are you doing 1/X divides? are the results of this fed into a multiplier? why not just do Y/X in the first instance?

12+ hours of RTL compile is far far far too long. The longest Ive ever seen (for a very full stratix 4) was 1 hour (with 4-8 hours fit). Do you have some rams that are actually being synthesised as registers? that is usually the culprit for long synthesis (and would then result in a very full and congested chip).