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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
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Altera_Forum
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10 years ago

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... but when divisors (100+) are synthetized ...

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Wow, 100+ dividers! There could be room for improvement? Are all numerators truly dynamic, or are some loaded by the application, or are some constant?

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