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Altera_Forum
Honored Contributor
10 years agoQuartus Router Congestion
Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_Forum
Honored Contributor
10 years agoNobody else asked so I will. Any chance you can move to a larger device, like an Arria V? Or split the design into two C5s? Stuffing a device to 99% full can be a costly endeavor. Even if you spend the NRE now to squeeze it in, if you ever need to add logic or even fix a bug, you could be in trouble. And with the device that full using SignalTap is impossible. Even if you verify everything in simulation, SignalTap can still be a lifesaver when unexpected things happen in hardware.
I got stuck in this situation once in an Arria II device (99% full) because system requirements changed over time. For a while we got away with it. Then over time a couple of changes were made and it started to fail timing, so I had to slow down the memory clock. Then eventually it just would no longer fit. The extra cost of using a larger device to start with would have been a huge cost savings in the end. And we eventually ended up there anyway. If this is just a prototype or hobby project then have at it and good luck. But going into production with that part 99% full would be extremely risky.