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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

That sounds highly inefficient. Can't you insert data during run time? What latency is required? If you don't care about latency then you could re use as much logic s you wanted.