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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I don't have as long as I want, it is on FPGA to speed up so I try to get max performance :)

Clearly one day this will go into Stratix/Arria devices OR multiple Cyclone devices but I want to close a demo with just a Cyclone V for demonstration. I don't use 99% but 81% that seem reasonable. Then 14% of ALM are unavailable due to congestion :(

By design routing "should" be simple but when divisors (100+) are synthetized with Synplify with pipeline inferred with retiming problem arise.. (12+ hours of RTL compilation + Fitter that fail after 1+ hour).. too things packed.. I have to try to use LPM_DIV with pipeline but this isn't a great option for "portability" of system.