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Altera_Forum
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10 years ago

Quartus Router Congestion

Hello all, I have a Cyclone V A9 device (300k LEs) and a big design that fit it 95% ALM 12% Memory bits 37% DSP. 14% of ALM are unavailable due to LAB input limits and wide-signals conflicts so...
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Altera_Forum
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10 years ago

12 hours of RTL compilation? That seems way, way too long. Can you do partitions(I think they have another name for it) in Synplify to reduce that?