QSYS simulation error when using VHDL testbench simulation model

Hi, I have a similar issue: when I try to simulate with Verilog, everything is ok, while with VHDL there is some problem.

I think the problem is related to Altera Avalon BFM, that only support Verilog.

Did you find any alternatives?

Thanks

Luca

Hello,

in my case the problem was related to the window paths exceeding the ~260 limit.

Make sure the path name for the Quartus project, QSYS output generation directory and Nios II project name are as short as possible so that the total path name will not exceed window path limit.

Also, Quartus 13.0 now has a key new feature, it now (finally) supports VHDL bus functional models (BFMs)

Saber890

--- Quote Start ---

Hello,

in my case the problem was related to the window paths exceeding the ~260 limit.

Make sure the path name for the Quartus project, QSYS output generation directory and Nios II project name are as short as possible so that the total path name will not exceed window path limit.

Also, Quartus 13.0 now has a key new feature, it now (finally) supports VHDL bus functional models (BFMs)

Saber890

--- Quote End ---

Yes, thank you very much. This was the annoying problem :-)

Very stumbling!

Luca

Hi,

What were Altera thinking?

They don't do this to the Verilog users.

Looking at the ERROR on:-

m1372899.blogspot.co.uk/2012/08/altera-qsys-eclipse-initialize-on-chip.html

Half way down the page.

This appears to be caused by:-

# ** Error: (vcom-1935) Unable to move temporary file

That is why vcom can't find it.

I think that this doesn't happen with ModelSim ASE.

Not for me anyway.

(So far, fingers crossed etc.)

ASE may be unaffected due to the PREcompiled VHDL Libraries.

I don't know about ModelSim AE.

I was thinking of upgrading to Mentor ModelSim for mixed Language Simulation of existing IP but the stupidly LONG PathNames & even just the MASSIVE FileNames give me great doubts.

Look at the Error Msg posted by saber890.

Part of the problem is that the name that is given to the QSYS System appears THREE times in the PathName

So with the name that was chosen which was niosii_system, that adds 39 chars to the PathName because it is 13 chars by itself.

But that is not the WORST part, you also get:-

niosii_system_nios2_instruction_master_translator_avalon_universal_master_0_agent.vho

This is an EIGHTY NINE char FileName.

The resulting PathName is 165 chars LONG.

C:/an35_design/niosii_system/testbench/niosii_system_tb/simulation/submodules/niosii_system_nios2_instruction_master_translator_avalon_universal_master_0_agent.vho

Anyway, back to the other example:-

m1372899.blogspot.co.uk/2012/08/altera-qsys-eclipse-initialize-on-chip.html

C:/Users/cm78/Documents/Altera/projects/20120807testqsys/software/test_mem_windows/obj/default/runtime/sim/mentor/libraries/qsys_nios_system_tb_uart_0_s1_translator_avalon_universal_slave_0_agent/_temp/vloghrrwre

is 213 chars LONG

&

C:/Users/cm78/Documents/Altera/projects/20120807testqsys/software/test_mem_windows/obj/default/runtime/sim/mentor/libraries/qsys_nios_system_tb_uart_0_s1_translator_avalon_universal_slave_0_agent/qsys_nios_system_uart_0_s1_translator_avalon_universal_slave_0_agent/_primary.dbs

is 278 chars LONG

Soooooooooooooo

The command to move that file is about

500 chars LONG

so you can't be surprised when on Windows you get:-

# ** Error: (vcom-1935) Unable to move temporary file

I suppose it may be possible to PREcompile the QSYS VHDL Libraries if I get the full version of ModelSim from Mentor.

(The Simulation Lib Compiler in Quartus obviously DOESN'T PREcompile the QSYS files that are causing the problems)

Does anyone reading this know how to do that?

Please let us know.

The PREcompiled VHDL Libs that come with ModelSim ASE have worked so far for me.

......................................................

Altera, you have gone mad with these LONG PathNames.

Where were your minds when you did this?

No more EIGHTY NINE char FileNames please.

You didn't do this to the Verilog users so why do it to the VHDL users?

FIX IT!

In the meantime, post a TCL File to PREcompile Generated QSYS VHDL Files into Libraries for whatever version of Mentor ModelSim your customers are using.

AND a TCL File to make use of them in your customers projects.

You would almost think they hadn't tried this before releasing the tools!

>:-|

Nial.

Here is a Workaround from Altera:-

1. Backup the msim_setup.tcl file which is located at ~an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor ditectory.

2. Open niosII 13.0 command shell and change the directory to <project directory>/an351_design

3. Type the following command and hit enter to compile the BFM source files into single library.

ip-make-simscript --spd=niosii_system_tb.spd --outputdirectory=./software/hello_world_an351/obj/default/runtime/sim --compile-to-work

Check page 7-37 of QSYS user guide for details about ip-make-simscript option:

altera.com/literature/hb/qts/qsys_intro.pdf

4. Next, copy line 58 and 59 of backup msim_setup.tcl and paste it into the new generated msim_setup.tcl file.

For example:

file copy -force H:/CustomerDesign_2010/SR10960794/an351_design/software/hello_world_an351/mem_init/hdl_sim/niosii_system_ram.dat ./

file copy -force H:/CustomerDesign_2010/SR10960794/an351_design/software/hello_world_an351/mem_init/niosii_system_ram.hex ./

5. Right click on the hello _world_an351 in project explorer. Point to run as and then click Nios II Modelsim to rerun the simulation. I have verified. It works now. I attach my project as your reference. Please go to ~\an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor\ directory to view the msim_setup.tcl file for details.