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Altera_Forum's avatar
Altera_Forum
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13 years ago

QSYS simulation error when using VHDL testbench simulation model

Hi, I'm running a simulation on a simple QSYS system. The QSYS system is the same as the one used in the AN351 application "Simulating Nios II Embedded Processor Designs", having a clock...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello,

in my case the problem was related to the window paths exceeding the ~260 limit.

Make sure the path name for the Quartus project, QSYS output generation directory and Nios II project name are as short as possible so that the total path name will not exceed window path limit.

Also, Quartus 13.0 now has a key new feature, it now (finally) supports VHDL bus functional models (BFMs)

Saber890