QSYS simulation error when using VHDL testbench simulation model

Here is a Workaround from Altera:-

1. Backup the msim_setup.tcl file which is located at ~an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor ditectory.

2. Open niosII 13.0 command shell and change the directory to <project directory>/an351_design

3. Type the following command and hit enter to compile the BFM source files into single library.

ip-make-simscript --spd=niosii_system_tb.spd --outputdirectory=./software/hello_world_an351/obj/default/runtime/sim --compile-to-work

Check page 7-37 of QSYS user guide for details about ip-make-simscript option:

altera.com/literature/hb/qts/qsys_intro.pdf

4. Next, copy line 58 and 59 of backup msim_setup.tcl and paste it into the new generated msim_setup.tcl file.

For example:

file copy -force H:/CustomerDesign_2010/SR10960794/an351_design/software/hello_world_an351/mem_init/hdl_sim/niosii_system_ram.dat ./

file copy -force H:/CustomerDesign_2010/SR10960794/an351_design/software/hello_world_an351/mem_init/niosii_system_ram.hex ./

5. Right click on the hello _world_an351 in project explorer. Point to run as and then click Nios II Modelsim to rerun the simulation. I have verified. It works now. I attach my project as your reference. Please go to ~\an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor\ directory to view the msim_setup.tcl file for details.