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Altera_Forum
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13 years ago

QSYS simulation error when using VHDL testbench simulation model

Hi, I'm running a simulation on a simple QSYS system. The QSYS system is the same as the one used in the AN351 application "Simulating Nios II Embedded Processor Designs", having a clock...
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Altera_Forum
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12 years ago

Hi, I have a similar issue: when I try to simulate with Verilog, everything is ok, while with VHDL there is some problem.

I think the problem is related to Altera Avalon BFM, that only support Verilog.

Did you find any alternatives?

Thanks

Luca