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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem when Convert Verilog into VHDL

Hi,

I am trying to convert verilog into VHDL by my self. But I am totally confused by one thing.

My design receives one bit data from TDI when there is a rising edge of clock, then saves it into a 8-bit register by right-shifting, so TDI is transmitted as bytes. Then every byte is send to the output port.

I try to do the exactly same thing in both verilog and VHDL.However, by simulation report I found that verilog seems to ignore the first clock rising edge? It does nothing when the first rising edge arrives but VHDL code is triggered by the first rising edge.

I spend days on this problem but still cannot figure it out, please help me.

Please find my codes in attachment.

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I didn't look too much into the code but I notice one thing: the Verilog code only uses non-blocking assingments. while the VHDL code also uses variables.

    Assignments to VHDL variables behave like Verilog's blocking assignements.

    Assignments to VHDL signals behave like Verilog's non-blocking assignments.

    Maybe the issue lies there. Have you tried to convert the code using only VHDL signals instead of variables?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I can't indentify at first look the functional differences between both designs. It seems, that the different behaviour of variable assignments has been compensated by reordering the statements.

    But rbugalho is completely right. Using signals as the VHDL equivalent to non-blocking Verilog assignments, you can simply translate the code line-by-line, without needing to reorder anything.

    By the way, X-HDL is doing a good job in translating Verilog to VHDL and vice-versa. http://www.x-tekcorp.com/xhdl.php
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thank you rbugalho and FvM.Now blocking assignment and nonblocking assignment are clear to me.

    FvM,I'm afraid that X_HDL is not for free. If it is free could you send me a link that I can download and install the sw?Because what I found requires lisence.

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    No, it's not for free. I mentioned it, because there has been a previous Altera Forum discussion, if automatic HDL translation would be possible.

    In the meantime, I was aware of X-HDL and saw some promising results, but I'm not presently using it.

    I'm keeping my opinion, that manual translation is basically easy, but time consuming for larger IP, of course.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Could you help me with this line of code?

    The following is in Verilog:

    always@(posedge TCK or posedge TCS)

    begin

    ...

    end

    I don't know how to write the same thing in VHDL...:confused:
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    always@(posedge TCK or posedge TCS)

    begin

    ...

    end

    --- Quote End ---

    is actually ambiguous, because the meaning of Verilog posedge depends on the following code. But it makes sense only in this form: 

    always@(posedge TCK or posedge TCS)
begin
  if (TCS)
  ...
  else
  ...
end

    The respective VHDL equivalent is 

    process(TCS,TCK)
begin
  if TCS = '1' then
  elsif rising_edge(TCK)
  end if;
end;

    You'll find various Altera Forum threads discussing the same. Also Quartus HDL templates can help you to understand the basic concepts of both languages.

    I guess, you understand, that the asynchronous processing of TCS in the present code creates a different behaviour than your previous posting.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The design doesn't work, the outputs don't depend on any input signal.

    That's not surprizing, because you commented out a lot of most likely required code.