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Altera_Forum
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16 years ago

Problem when Convert Verilog into VHDL

Hi, I am trying to convert verilog into VHDL by my self. But I am totally confused by one thing. My design receives one bit data from TDI when there is a rising edge of clock, then saves it into...
Altera_Forum's avatar
Altera_Forum
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16 years ago

No, it's not for free. I mentioned it, because there has been a previous Altera Forum discussion, if automatic HDL translation would be possible.

In the meantime, I was aware of X-HDL and saw some promising results, but I'm not presently using it.

I'm keeping my opinion, that manual translation is basically easy, but time consuming for larger IP, of course.