--- Quote Start ---
always@(posedge TCK or posedge TCS)
begin
...
end
--- Quote End ---
is actually ambiguous, because the meaning of Verilog posedge depends on the following code. But it makes sense only in this form:
always@(posedge TCK or posedge TCS)
begin
if (TCS)
...
else
...
end
The respective VHDL equivalent is
process(TCS,TCK)
begin
if TCS = '1' then
elsif rising_edge(TCK)
end if;
end;
You'll find various Altera Forum threads discussing the same. Also Quartus HDL templates can help you to understand the basic concepts of both languages.
I guess, you understand, that the asynchronous processing of TCS in the present code creates a different behaviour than your previous posting.
Honored Contributor
