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Altera_Forum
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16 years ago

Problem when Convert Verilog into VHDL

Hi, I am trying to convert verilog into VHDL by my self. But I am totally confused by one thing. My design receives one bit data from TDI when there is a rising edge of clock, then saves it into...
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Altera_Forum
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16 years ago

I can't indentify at first look the functional differences between both designs. It seems, that the different behaviour of variable assignments has been compensated by reordering the statements.

But rbugalho is completely right. Using signals as the VHDL equivalent to non-blocking Verilog assignments, you can simply translate the code line-by-line, without needing to reorder anything.

By the way, X-HDL is doing a good job in translating Verilog to VHDL and vice-versa. http://www.x-tekcorp.com/xhdl.php