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Altera_Forum
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16 years ago

Problem when Convert Verilog into VHDL

Hi, I am trying to convert verilog into VHDL by my self. But I am totally confused by one thing. My design receives one bit data from TDI when there is a rising edge of clock, then saves it into...
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Altera_Forum
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16 years ago

I didn't look too much into the code but I notice one thing: the Verilog code only uses non-blocking assingments. while the VHDL code also uses variables.

Assignments to VHDL variables behave like Verilog's blocking assignements.

Assignments to VHDL signals behave like Verilog's non-blocking assignments.

Maybe the issue lies there. Have you tried to convert the code using only VHDL signals instead of variables?