No output depends on input (outputs stuck at VCC or GND) errors

Yes. I introduced this mistake before posting. Unfortunately it is not the cause of my issue.

Even with this mistake fixed my logic is being optimized away.

I can try that, but I haven't had an issue combining state and output logic in the past. When I simulate the design as-is the logic works fine.

(hopefully this snapshot is readable when uploaded)

Under optimization results I see:

This paper (http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf) also makes use of a don't care state to account for the unused states in the typedef state enumeration. I have used this coding style before without issue.

I'm unfamiliar with creating a state machine encoding assignment, but I do know that a state machine is being inferred by this code as it appears as designed in the "Analysis and Synthesis - State Machine" output.

It turns out that my issue was caused by using 'x in my typedef state enum after all.

Something must have changed, or this project's settings are slightly different in some way because I have used this construct successfully before.

typedef enum logic [4:0] {
S_REBOOT = 5'b0_0001,
S_GROUP_1_EN = 5'b0_0010,
S_GROUP_2_EN = 5'b0_0100,
S_GROUP_3_EN = 5'b0_1000,
S_PS_DONE = 5'b1_0000,
S_FSM_ERROR = 'x <-- Removing this fixed my issue.
} state_e;
state_e state;

I then decided to add in another state for error catching (the default case switch sends the FSM to this state) and let the compiler assign enum values automatically:

localparam STATE_NUM = 6;
typedef enum logic [STATE_NUM - 1 : 0] {
S_REBOOT,
S_GROUP_1_EN,
S_GROUP_2_EN,
S_GROUP_3_EN,
S_PS_DONE,
S_FSM_ERROR
} state_e;
state_e state;

I added the "State Machine Processing" assignment, but am still seeing the issue.

I think a big part of my problem is that the project doesn't think that "Clock_25MHz_Max10" or "RESETn" have outputs that are dependent on them. I've tried using "Clock_25MHz_Max10" directly by bypassing the PLL. I've tried adding "set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "Clock_25MHz_Max10" " into my .qsf.

Could the .sdc cause this isue?

At the moment I have an .sdc that has:

set_time_format -unit ns -decimal_places 3

create_clock -period 40 [get_ports Clock_25MHz_Max10]

derive_pll_clocks

derive_clock_uncertainty