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cdmski's avatar
cdmski
Icon for New Contributor rankNew Contributor
3 years ago
Solved

No output depends on input (outputs stuck at VCC or GND) errors

I'm attempting to implement simple power sequencing logic in a MAX10 fpga. There are four groups of power regulators that are enabled sequentially when the each regulator in the preceding group sup...
  • sstrell's avatar
    sstrell
    3 years ago

    Weird. Other things I notice: you have 6 states, but you set S_FSM_ERROR as 'x (and only using 5 bits for the state). It should probably have a defined value. Also, even though you are manually doing one-hot encoding here, did you create a state machine encoding assignment in the Assignment Editor?

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Create a "State Machine Processing" assignment in the Assignment Editor and set the encoding style appropriately.

cdmski's avatar
cdmski
Icon for New Contributor rankNew Contributor
3 years ago

I added the "State Machine Processing" assignment, but am still seeing the issue.

I think a big part of my problem is that the project doesn't think that "Clock_25MHz_Max10" or "RESETn" have outputs that are dependent on them. I've tried using "Clock_25MHz_Max10" directly by bypassing the PLL. I've tried adding "set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "Clock_25MHz_Max10" " into my .qsf.

Could the .sdc cause this isue?

At the moment I have an .sdc that has:

set_time_format -unit ns -decimal_places 3

create_clock -period 40 [get_ports Clock_25MHz_Max10]

derive_pll_clocks

derive_clock_uncertainty