Forum Discussion
cdmski
New Contributor
New ContributorNo output depends on input (outputs stuck at VCC or GND) errors
I'm attempting to implement simple power sequencing logic in a MAX10 fpga.
There are four groups of power regulators that are enabled sequentially when the each regulator in the preceding group sup...
Weird. Other things I notice: you have 6 states, but you set S_FSM_ERROR as 'x (and only using 5 bits for the state). It should probably have a defined value. Also, even though you are manually doing one-hot encoding here, did you create a state machine encoding assignment in the Assignment Editor?
sstrell
Super Contributor
Super ContributorYour clock naming is mismatched. In the top-level port mapping, you call the clock ip_clk_25 but in the power sequencer, it's call ip_clk.
cdmskiNew Contributor
New ContributorYes. I introduced this mistake before posting. Unfortunately it is not the cause of my issue.
Even with this mistake fixed my logic is being optimized away.
