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cdmski's avatar
cdmski
Icon for New Contributor rankNew Contributor
3 years ago
Solved

No output depends on input (outputs stuck at VCC or GND) errors

I'm attempting to implement simple power sequencing logic in a MAX10 fpga. There are four groups of power regulators that are enabled sequentially when the each regulator in the preceding group sup...
  • sstrell's avatar
    sstrell
    3 years ago

    Weird. Other things I notice: you have 6 states, but you set S_FSM_ERROR as 'x (and only using 5 bits for the state). It should probably have a defined value. Also, even though you are manually doing one-hot encoding here, did you create a state machine encoding assignment in the Assignment Editor?

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Something to try: normally for a state machine, you use two separate processes: a clocked process for the next state logic and a combinatorial process for the outputs. Because you've combined these and you are using non-blocking assignments for what should be combinatorial logic, it's possible the outputs are not getting updated as expected. Try separating out the processes.

  • cdmski's avatar
    cdmski
    Icon for New Contributor rankNew Contributor
    3 years ago

    I can try that, but I haven't had an issue combining state and output logic in the past. When I simulate the design as-is the logic works fine.

    (hopefully this snapshot is readable when uploaded)

    Under optimization results I see: