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cdmski's avatar
cdmski
Icon for New Contributor rankNew Contributor
3 years ago
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No output depends on input (outputs stuck at VCC or GND) errors

I'm attempting to implement simple power sequencing logic in a MAX10 fpga. There are four groups of power regulators that are enabled sequentially when the each regulator in the preceding group sup...
  • sstrell's avatar
    sstrell
    3 years ago

    Weird. Other things I notice: you have 6 states, but you set S_FSM_ERROR as 'x (and only using 5 bits for the state). It should probably have a defined value. Also, even though you are manually doing one-hot encoding here, did you create a state machine encoding assignment in the Assignment Editor?

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Weird. Other things I notice: you have 6 states, but you set S_FSM_ERROR as 'x (and only using 5 bits for the state). It should probably have a defined value. Also, even though you are manually doing one-hot encoding here, did you create a state machine encoding assignment in the Assignment Editor?

cdmski's avatar
cdmski
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3 years ago

This paper (http://www.sunburst-design.com/papers/CummingsSNUG2019SV_FSM1.pdf) also makes use of a don't care state to account for the unused states in the typedef state enumeration. I have used this coding style before without issue.

I'm unfamiliar with creating a state machine encoding assignment, but I do know that a state machine is being inferred by this code as it appears as designed in the "Analysis and Synthesis - State Machine" output.